Metal interconnections may be used to make electrical connections between devices or between interconnections. Although aluminum (Al) or tungsten (W) may be used for metal interconnections, alternative metallic materials having adequate electrical characteristic may be necessary in highly integrated semiconductor devices, due to the relatively low melting point and/or relatively high specific resistivity of the Al or W. Copper (Cu) is a metallic material having relatively low specific resistivity and/or adequate reliability (e.g. reliable in electromigration and stress migration) for some applications. The melting point of Cu is relatively high at 1080° C. (compared to 660° C. for Al and 3400° C. for W) and the specific resistivity of Cu is relatively low at 1.7 μΩcm (compared to 2.7 μΩcm for Al and 5.6 μΩcm for W). A Cu alloy may also be used as a metal interconnection material instead of pure Cu. A Cu alloy that may be used should have a specific resistivity not much higher than pure Cu and should have adequate reliability and corrosion resistance characteristics.
It may be difficult to form a compound having strong volatility with Cu. Cu may be used in a damascene process, in which a trench (e.g. an interconnection) is formed. A trench may be formed by depositing an interlayer insulating film, etching the insulating film (e.g. through photolithography), filling the trench with Cu, and/or planarizing the Cu (e.g. by chemical mechanical polishing (CMP)). A dual damascene process may form vias and metal interconnections in multi-layered interconnection structures.
Example FIGS. 1A through 1G are cross-sectional views illustrating a method of forming a dual damascene interconnection in a semiconductor device. As illustrated in example FIG. 1A, a silicon carbide (SiC) film may be formed as etch stop film 120 over first metal interconnection film 110. First metal interconnection film 110 may be formed in lower insulating film 100. First and second insulating films 130a and 130b may be sequentially formed over etch stop film 120.
As illustrated in example FIG. 1B, a via hole 140 (which may expose etch stop film 120) may pass through first and second insulating films 130a and 130b. Via hole 140 may be formed through an etching process using a predetermined mask film pattern (e.g. a photoresist pattern). After via hole 140 has been formed, a mask film pattern may be removed through a stripping process.
As illustrated in example FIG. 1C, a sacrificial film 150 may be formed in via hole 140. Sacrificial film 150 may protect via hole 140 when forming a trench in a subsequent process. A recess process may be performed to remove an upper portion of sacrificial film 150. A Novolac gap-fill material may be used as the sacrificial film 150 and the Novolac gap-fill material may be recessed from a surface of via hole 140 to a predetermined depth.
As illustrated in example FIG. 1D, a mask film pattern 160 may be formed on the surface of second insulating film 130b. Trench 170 may be formed through an etching process using mask film pattern 160 as an etching mask.
As illustrated in example FIG. 1E, mask film pattern 160 may be removed through an ashing process. Sacrificial film 150 remaining in via hole 140 may also be removed.
As illustrated in example FIG. 1F, a portion of etch stop film 120 that is exposed through the via hole 140 may be removed. As illustrated in example FIG. 1G, Cu may fill the via hole 140 and trench 170 to form a second metal interconnection film 180. Second metal interconnection film 180 may contact first metal interconnection film 110. Before filling the via hole 140 and the trench 170 with Cu, a barrier metal (e.g. a Ta/TaN film) may be deposited inside via hole 140 and trench 170.
Cu and/or barrier metal formed over a top surface of inter-metal insulating film 130 may be removed through a planarization process (e.g. by planarizing the Cu and/or barrier metal through a CMP process until the inter-metal insulating film 130 is exposed) to form second metal interconnection film 180 connected vertically to first metal interconnection film 110.
However, when forming a metal interconnection using a dual damascene process, a via hole may be protected when etching an overlying trench by a gap-fill material in the via hole. Multiple process may need to be performed to recess the gap-fill material and then fully remove the gap-fill material from the via hole (after the trench is formed). Such multiple processes may make semiconductor fabrication overly complicated.